Ultra-low-power radio receivers have very tight power budgets, for example, 100 μW in wake-up receivers. The tight power budget in those receivers limits multichannel capabilities and blocker robustness. Digitization and digital signal processing (DSP) present an interesting solution, and can further enable interferer-resilient spread spectrum techniques. However, digitization and DSP demand an analog-to-digital converter (ADC) to digitize analog samples, for example, in the 10 MHz-50 MHz intermediate frequency (IF) bandwidth (BW) (bounded by the 1/f corner and the LO drift), while consuming only a few tens of μW with a modest Signal to Noise-plus-Distortion Ratio (SNDR). A Nyquist ADC cannot satisfy such a power constraint, because of its strict antialiasing filter specifications. Oversampling can simplify this requirement; however, a high sampling rate can result in a substantial power overhead, not just for the ADC, but also for subsequent processing blocks. Thus, there is a need for a power-efficient ADC with relaxed or no antialiasing constraints and a low output data rate.